Stabie-Soft Solutions

Scheture is our schematic capture package. The package is built atop the same database as all of the other Stabie-Soft products. The schematic editor handles iterated instances, bus'ed pins and wires, parameter passing etc.

The latest production version of Scheture is 3.3.8, please download it if your using an older version to get the latest updates and bug fixes.

The latest features include:

The ability to embed a PPM file in a schematic for your company logo.

Setting wire display width to wide or narrow if the wire is a bus or scaler during distilling.

Perhaps one of the best features is scheture's ability to generate a schematic (and symbols) from netlist formats such as verilog or spice. Take it for a 30 day test drive and see if it is right for you. See the pricing page for details on our free 30 day evaluations.
Pricing for per seat is only $700/yr.

A simple set of schematics along with the verilog and spice generated from them can be seen here. A couple more screen shots showing some graphics are here, here, here and here.

Features:
* User control of all object colors and fonts.
* Control of position, size, font, color of property display of symbols.
* A specific placement of a symbol may override property display position, size, font or color.
* Implicit connection of symbol pins by name possible for specific schematics.
** In the schematic here, note the bulk connections are made with this type of connection. No explicit connection to the bulk is drawn, but all unconnected bulks will be connected by name in this schematic only.
* Implicit global connection of symbol pins possible.
* Symbol properties may be set for display only (IE ignored by netlister).
* Symbol generator.
* Net tracing thru the hierarchy.
* Property values "push" down so "in context" display of properties displayed during descends thru the hierarchy.
* Extractor.
* Hierarchical verilog out.
* Hierarchical spice out.
** spice netlister has option for user defined processing of the parameters, allowing you to programmatically alter W, L etc.
* Hierarchical smash out. (For Dolphin's SMASH mixed mode simulator).
* Netlist to schematic generator to build a schematic from a netlist.
** Sample of nor3 and adder. Both these schematics were built completely automatically from spice netlists. Note verilog can also be auto generated for cross probing or visualization of hdl.
* Parasitic net schematic generator to visualize an extracted net's R/C network.
* Interfaces with Mentor's RVE product. Cross-probe between layout & schematic.
* Interfaces to open source waveform viewer GWave.
* User specified port order available for spice subcircuits and verilog primitives.
* Plotting, and includes a command to plot all schematics in a library.
* Sample library of symbols provided.
* Free upgrades after purchase